8085 microprocessor

Short notes on 8085 microprocessor 

• It has 8 bit ALU

• It has 8 bit data bus 
• It has 8 bit GPRS
• Data bus are bidirectional while address bus are unidirectional 
• It has 16 bit address bus that means it has 2^16 locations= 64kb 
• It has operating frequency 3.14Mhz nearly 3Mhz
• Crystal is connected to outside of the processor
• Operating freq. = (crystal freq. / 2)
• T_state = T_clk 
• Machine cycle = time taken to perform memory or I/O operations 
• Opcode fetch 4T
• Mem. Read & Write 3T states separately
• I/O read & write 3T states separately
• 1 T = 0.5 µsec means for 4T = 4*0.5µ=2µsec
• 8085
• 8 – 8 bit processor
• 8 – 8  h/w interrupts
• 5 – 5 S/W interrupts
• Multiplexing is used to reduce the pins but also decrease the speed of processor
• A0 to A7 add. Bits are multiplexed with D0 to D7 data bits 
• ALE(address latch enable) when ALE =1 then A0 to A7 are active when ALE = 0 D0 to D7 are active
• Interrupt is a signal on h/w pin(H/W intr.)
• transfer the pgm instruction from current location to new location is s/w int.
• 5 h/w interrupt are 
 1) TRAP(HIGHEST PRIORITY)
 2) RST 7.5
 3) RST 6.5
 4) RST 5.5
 5) INTR
• 8 S/W interrupt are RST 0 to RST 7
 RST 0 TO RST 7
• ISR(INTERRUPT SERVICE ROUTINE ) is a new pgm when interrupt is occur
• Vectored interrupt have starting address is fixed 
• All interrupts are vectored expect INTR is non-vectored 
• Starting add. are calculate as for RST 7.5 (7.5*8=60---003Ch) likely same with others
• All interrupt are maskable expect TRAP
• EI(Enable interrupt control ) = 1 All interrupts are enabled with maskable property
• DI(Disable interrupt control) =0 All interrupts are disabled expect TRAP
• TRAP is always Enabled interrupt
• TRAP is level and edge triggered interrupt
• RST 7.5 is edge triggered interrupt while all others are level triggered interrupt
• 8085 µp support DMA(direct memory access)[that’s transpiring the data from I/O to memory without interfacing the microprocessor]
• 8085 has internal serial port
• Pin details 
 It is 40 pin IC
 Uses NMOS TECH
 29000 Transistors
 5V supply
• S1 & S0 shows the current status of the processor
 S1 S0
 1 1--opcode fetch
 1 0 -read operation
 0 1 -write operation 
 0 0 interrupt ack cycle
• READY instruction used to synchronize slower peripheral to microprocessor GPRS
• It has 6 GPRS(general purpose registers )B,C,D,E,H,L All are 8 bits
• SP & PC are special purpose registers of 16 bits 
• PC(program counter )is used to store add. of next execution instruction
• Stack is used to store temporary data & Add. of ISR
• In push operation SP Always hold the add. of the top of the stack
• Firstly decrement the stack & then store the Higher byte And decrement stack & the store the Lower byte of stack 
• SP is a 16 bit register
• In 8085 there are256 instructions