ARM VS AVR

ARM7TDMI:thumb2 instruction set it is 2 bytes  some 4 bytes
thumb2 arm+thumb
total 37 registers
R0-R15 general purpose
R13 stack
R14 Link( lr (or r14) is used as a link register to store the return address)

by default data abort is handled when an application read or write an illegal memory location. You can calculate the illegal memory location using by subtracting 8 from the value in R14 (link register).

Exceptions are processed in ARM state

The SWI instruction causes a SWI exception. This means that the processor state changes to ARM, the processor mode changes to Supervisor, the CPSR is saved to the Supervisor Mode SPSR, and execution branches to the SWI vector


ARMCM3: two states
*debug state
*thumb state
16 registers
13 GP
3 special purpose
The ARM7TDMI core has a Von Neumann architecture, with a single 32-bit data bus carrying both instructions and data.

The ARM9TDMI processor core is a Harvard architecture device implemented using a five-stage pipeline consisting of Fetch, Decode, Execute, Memory, and Write stages.

ARM has full stack descending

• there are  1 to 15 exceptions
•  16 and above are external interrupt input
• interrupts has highest priority than the expections
•   there are some fix priority expections
• -3 --> Reset
• -2--->NMI
• -1--->Hard Fault
• programmable priority divided into two halves
• upper half(left bits) is the preempt priority
• lower half(right bits) is the subpriority
• upto 256 levels of programmable priority
• two buses in CM3
• I(instruction)-code bus:
• it is used to access instructions from flash memory
• D(data)-code bus:
• it is useds to access data from flash memory.
• system bus(AHB):
• used to connect SRAM,peripherals
• PPB(APB):
• it is used to connect builtin components like debug unit,systick timer, NVIC
• SPI is full duplex
• I2C half duplex
• I2C has 7bit address that means only 120 devices are connected at a time
• RS232 is a full duplex protocol
• RSB R0,R1,#0 it means subtract from zero make 2's compliment of R1
• ADCS R1,R1,R2 add with carry
• MVN instruction in ARM copy Rd and perform not operation on it
• STMFD r13!,{r0-r5} push the value into full descending stack
• LCMFD r13!,{r0-r5} pop the value from full descending stack
• 
  

AVR: it uses FLASH memory
There are 32 general-purpose 8-bit registers, R0–R31
The last three register pairs are used as pointer registers for memory addressing. They are known as X (R27:R26), Y (R29:R28) and Z (R31:R30).
ATmega32 has 2K memory 32 pin
In AVR program counter is 16bit wide
AVR has empty stack descending implementing 
AVR program memory is divided into 2 section
SET instruction is used to enable the interrupt
in AVR when interrupt is occur 1st up of all current instruction is executed first and then address of next instruction is store onto stack

In AVR microcontroller, critical section is achieved by the following combination of instructions first CLI and second is SEI

SPI:
Clock polarity (CPOL) and clock phase (CPHA) are the main parameters that define a clock format to be used by the SPI bus. 
CPOL: (clock priority)0 is noninverted clock,
CPOL:1 is inverted clock
CPHA:(Clock phase)0 capture the data from starting clock pulse
CPHA:1 capture the data from second clock pulse 
To operate SPI in Master mode
MSTR 1
CPOL:0
CPHA:1


stop condition in I2c is 
SCL line is high,SDA is goes from low to high

recessive bit in CAN represent logical 1
dominant bit in CAN represent logical 0